Populate repository from main eagle directory in user's document library.

4 files changed, 828 insertions, 0 deletions

diff --git a/eagle/lbr/atmega/at24mac402.lbr b/eagle/lbr/atmega/at24mac402.lbr
new file mode 100755
index 0000000..30b039e
--- /dev/null
+++ b/eagle/lbr/atmega/at24mac402.lbr
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
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+<text x="-5.08" y="5.08" size="1.27" layer="21">&gt;NAME</text>
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+</package>
+</packages>
+<symbols>
+<symbol name="AT24MAC402">
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+<pin name="GND" x="-15.24" y="-12.7" length="middle" direction="pwr"/>
+<pin name="SDA" x="15.24" y="7.62" length="middle" rot="R180"/>
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+<text x="-5.6642" y="-21.3614" size="2.0828" layer="96" ratio="10" rot="SR0">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="24MAC402-SSHM-T" prefix="U">
+<description>EEPROM, SERIAL, 2KB, 48-BIT MAC, 8SOIC</description>
+<gates>
+<gate name="A" symbol="AT24MAC402" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SOIC127P600X175-8N">
+<connects>
+<connect gate="A" pin="A0" pad="1"/>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="GND" pad="4"/>
+<connect gate="A" pin="SCL" pad="6"/>
+<connect gate="A" pin="SDA" pad="5"/>
+<connect gate="A" pin="VCC" pad="8"/>
+<connect gate="A" pin="WP" pad="7"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MPN" value="24MAC402-SSHM-T" constant="no"/>
+<attribute name="OC_FARNELL" value="2134868" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+<attribute name="PACKAGE" value="8SOIC" constant="no"/>
+<attribute name="SUPPLIER" value="ATMEL" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="PDIP" package="PDIP">
+<connects>
+<connect gate="A" pin="A0" pad="1"/>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="GND" pad="4"/>
+<connect gate="A" pin="SCL" pad="6"/>
+<connect gate="A" pin="SDA" pad="5"/>
+<connect gate="A" pin="VCC" pad="8"/>
+<connect gate="A" pin="WP" pad="7"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>
diff --git a/eagle/lbr/atmega/atmega328.lbr b/eagle/lbr/atmega/atmega328.lbr
new file mode 100755
index 0000000..080bd3d
--- /dev/null
+++ b/eagle/lbr/atmega/atmega328.lbr
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.3">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
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+<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/>
+<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="128" name="_bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/>
+<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/>
+<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="150" name="Notes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="152" name="_bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="153" name="FabDoc1" color="6" fill="1" visible="no" active="no"/>
+<layer number="154" name="FabDoc2" color="2" fill="1" visible="no" active="no"/>
+<layer number="155" name="FabDoc3" color="7" fill="15" visible="no" active="no"/>
+<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="201" name="201bmp" color="2" fill="1" visible="no" active="no"/>
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+<layer number="250" name="Descript" color="7" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="7" fill="1" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<packages>
+<package name="DIL28-3">
+<description>&lt;B&gt;Dual In Line&lt;/B&gt;&lt;p&gt;
+package type P</description>
+<wire x1="-17.78" y1="-1.27" x2="-17.78" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-17.78" y1="1.27" x2="-17.78" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
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+<wire x1="-17.653" y1="-2.54" x2="17.78" y2="-2.54" width="0.1524" layer="21"/>
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+<pad name="28" x="-16.51" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-17.907" y="-2.54" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-15.748" y="-0.9398" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="DIL28-3-ROUND">
+<wire x1="-18.542" y1="-0.635" x2="-18.542" y2="-2.794" width="0.1524" layer="21"/>
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+<pad name="18" x="8.89" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<pad name="19" x="6.35" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<pad name="20" x="3.81" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<pad name="21" x="1.27" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<pad name="22" x="-1.27" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<pad name="23" x="-3.81" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
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+<pad name="28" x="-16.51" y="3.81" drill="0.8128" diameter="1.6764" rot="R90"/>
+<text x="-19.2024" y="-2.54" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-15.875" y="-0.635" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="MEGA328">
+<wire x1="-17.78" y1="30.48" x2="27.94" y2="30.48" width="0.254" layer="94"/>
+<wire x1="27.94" y1="30.48" x2="27.94" y2="-35.56" width="0.254" layer="94"/>
+<wire x1="27.94" y1="-35.56" x2="-17.78" y2="-35.56" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="-35.56" x2="-17.78" y2="30.48" width="0.254" layer="94"/>
+<text x="-17.78" y="-40.64" size="1.778" layer="95">&gt;NAME</text>
+<text x="-5.08" y="33.02" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="(PCI5/SCK)PB5" x="33.02" y="-33.02" length="middle" rot="R180"/>
+<pin name="PB7(XTAL2/TOSC2/PCI7)" x="-22.86" y="5.08" length="middle"/>
+<pin name="PB6(XTAL1/TOSC1/PCI6)" x="-22.86" y="10.16" length="middle"/>
+<pin name="GND" x="-22.86" y="-2.54" length="middle"/>
+<pin name="VCC" x="-22.86" y="-7.62" length="middle"/>
+<pin name="AGND" x="-22.86" y="22.86" length="middle"/>
+<pin name="AREF" x="-22.86" y="20.32" length="middle"/>
+<pin name="AVCC" x="-22.86" y="17.78" length="middle"/>
+<pin name="(PCI4/MISO)PB4" x="33.02" y="-30.48" length="middle" rot="R180"/>
+<pin name="(PCI3/MOSI/OC2A)PB3" x="33.02" y="-27.94" length="middle" rot="R180"/>
+<pin name="(PCI2/SS/OC1B)PB2" x="33.02" y="-25.4" length="middle" rot="R180"/>
+<pin name="(PCI1/OC1A/OC1S)PB1" x="33.02" y="-22.86" length="middle" rot="R180"/>
+<pin name="(PCI0/ICP/CLKO)PB0" x="33.02" y="-20.32" length="middle" rot="R180"/>
+<pin name="(PCI23/AIN1)PD7" x="33.02" y="-15.24" length="middle" rot="R180"/>
+<pin name="(PCI22/AIN0OC0A)PD6" x="33.02" y="-12.7" length="middle" rot="R180"/>
+<pin name="(PCI21/T1/OC0B)PD5" x="33.02" y="-10.16" length="middle" rot="R180"/>
+<pin name="(PCI20/XCK/T0)PD4" x="33.02" y="-7.62" length="middle" rot="R180"/>
+<pin name="(PCI19/INT1/OC2B)PD3" x="33.02" y="-5.08" length="middle" rot="R180"/>
+<pin name="(PCI18/INT0)PD2" x="33.02" y="-2.54" length="middle" rot="R180"/>
+<pin name="(PCI17/TXD)PD1" x="33.02" y="0" length="middle" rot="R180"/>
+<pin name="(PCI16/RXD)PD0" x="33.02" y="2.54" length="middle" rot="R180"/>
+<pin name="(PCI13/ADC5/SCL)PC5" x="33.02" y="15.24" length="middle" rot="R180"/>
+<pin name="(PCI12/ADC4/SDA)PC4" x="33.02" y="17.78" length="middle" rot="R180"/>
+<pin name="(PCI11/ADC3)PC3" x="33.02" y="20.32" length="middle" rot="R180"/>
+<pin name="(PCI10/ADC2)PC2" x="33.02" y="22.86" length="middle" rot="R180"/>
+<pin name="(PCI9/ADC1)PC1" x="33.02" y="25.4" length="middle" rot="R180"/>
+<pin name="(PCI8/ADC0)PC0" x="33.02" y="27.94" length="middle" rot="R180"/>
+<pin name="PC6(/RESET/PCI14)" x="-22.86" y="27.94" length="middle" function="dot"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATMEGA328*P" prefix="IC">
+<description>&lt;b&gt;MICROCONTROLLER&lt;/b&gt;&lt;p&gt;
+32 kBytes FLASH&lt;p&gt;
+2 kBytes SRAM&lt;p&gt;
+1 kBytes EEPROM&lt;p&gt;
+USART&lt;p&gt;
+8-channel 10 bit ADC&lt;p&gt;</description>
+<gates>
+<gate name="G$1" symbol="MEGA328" x="-5.08" y="0"/>
+</gates>
+<devices>
+<device name="" package="DIL28-3">
+<connects>
+<connect gate="G$1" pin="(PCI0/ICP/CLKO)PB0" pad="14"/>
+<connect gate="G$1" pin="(PCI1/OC1A/OC1S)PB1" pad="15"/>
+<connect gate="G$1" pin="(PCI10/ADC2)PC2" pad="25"/>
+<connect gate="G$1" pin="(PCI11/ADC3)PC3" pad="26"/>
+<connect gate="G$1" pin="(PCI12/ADC4/SDA)PC4" pad="27"/>
+<connect gate="G$1" pin="(PCI13/ADC5/SCL)PC5" pad="28"/>
+<connect gate="G$1" pin="(PCI16/RXD)PD0" pad="2"/>
+<connect gate="G$1" pin="(PCI17/TXD)PD1" pad="3"/>
+<connect gate="G$1" pin="(PCI18/INT0)PD2" pad="4"/>
+<connect gate="G$1" pin="(PCI19/INT1/OC2B)PD3" pad="5"/>
+<connect gate="G$1" pin="(PCI2/SS/OC1B)PB2" pad="16"/>
+<connect gate="G$1" pin="(PCI20/XCK/T0)PD4" pad="6"/>
+<connect gate="G$1" pin="(PCI21/T1/OC0B)PD5" pad="11"/>
+<connect gate="G$1" pin="(PCI22/AIN0OC0A)PD6" pad="12"/>
+<connect gate="G$1" pin="(PCI23/AIN1)PD7" pad="13"/>
+<connect gate="G$1" pin="(PCI3/MOSI/OC2A)PB3" pad="17"/>
+<connect gate="G$1" pin="(PCI4/MISO)PB4" pad="18"/>
+<connect gate="G$1" pin="(PCI5/SCK)PB5" pad="19"/>
+<connect gate="G$1" pin="(PCI8/ADC0)PC0" pad="23"/>
+<connect gate="G$1" pin="(PCI9/ADC1)PC1" pad="24"/>
+<connect gate="G$1" pin="AGND" pad="22"/>
+<connect gate="G$1" pin="AREF" pad="21"/>
+<connect gate="G$1" pin="AVCC" pad="20"/>
+<connect gate="G$1" pin="GND" pad="8"/>
+<connect gate="G$1" pin="PB6(XTAL1/TOSC1/PCI6)" pad="9"/>
+<connect gate="G$1" pin="PB7(XTAL2/TOSC2/PCI7)" pad="10"/>
+<connect gate="G$1" pin="PC6(/RESET/PCI14)" pad="1"/>
+<connect gate="G$1" pin="VCC" pad="7"/>
+</connects>
+<technologies>
+<technology name="-20"/>
+<technology name="V-10"/>
+</technologies>
+</device>
+<device name="ROUND" package="DIL28-3-ROUND">
+<connects>
+<connect gate="G$1" pin="(PCI0/ICP/CLKO)PB0" pad="14"/>
+<connect gate="G$1" pin="(PCI1/OC1A/OC1S)PB1" pad="15"/>
+<connect gate="G$1" pin="(PCI10/ADC2)PC2" pad="25"/>
+<connect gate="G$1" pin="(PCI11/ADC3)PC3" pad="26"/>
+<connect gate="G$1" pin="(PCI12/ADC4/SDA)PC4" pad="27"/>
+<connect gate="G$1" pin="(PCI13/ADC5/SCL)PC5" pad="28"/>
+<connect gate="G$1" pin="(PCI16/RXD)PD0" pad="2"/>
+<connect gate="G$1" pin="(PCI17/TXD)PD1" pad="3"/>
+<connect gate="G$1" pin="(PCI18/INT0)PD2" pad="4"/>
+<connect gate="G$1" pin="(PCI19/INT1/OC2B)PD3" pad="5"/>
+<connect gate="G$1" pin="(PCI2/SS/OC1B)PB2" pad="16"/>
+<connect gate="G$1" pin="(PCI20/XCK/T0)PD4" pad="6"/>
+<connect gate="G$1" pin="(PCI21/T1/OC0B)PD5" pad="11"/>
+<connect gate="G$1" pin="(PCI22/AIN0OC0A)PD6" pad="12"/>
+<connect gate="G$1" pin="(PCI23/AIN1)PD7" pad="13"/>
+<connect gate="G$1" pin="(PCI3/MOSI/OC2A)PB3" pad="17"/>
+<connect gate="G$1" pin="(PCI4/MISO)PB4" pad="18"/>
+<connect gate="G$1" pin="(PCI5/SCK)PB5" pad="19"/>
+<connect gate="G$1" pin="(PCI8/ADC0)PC0" pad="23"/>
+<connect gate="G$1" pin="(PCI9/ADC1)PC1" pad="24"/>
+<connect gate="G$1" pin="AGND" pad="22"/>
+<connect gate="G$1" pin="AREF" pad="21"/>
+<connect gate="G$1" pin="AVCC" pad="20"/>
+<connect gate="G$1" pin="GND" pad="8"/>
+<connect gate="G$1" pin="PB6(XTAL1/TOSC1/PCI6)" pad="9"/>
+<connect gate="G$1" pin="PB7(XTAL2/TOSC2/PCI7)" pad="10"/>
+<connect gate="G$1" pin="PC6(/RESET/PCI14)" pad="1"/>
+<connect gate="G$1" pin="VCC" pad="7"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>
diff --git a/eagle/lbr/atmega/in28j60.lbr b/eagle/lbr/atmega/in28j60.lbr
new file mode 100755
index 0000000..72cdc8a
--- /dev/null
+++ b/eagle/lbr/atmega/in28j60.lbr
@@ -0,0 +1,152 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
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+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
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+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<packages>
+<package name="DIL">
+<pad name="1" x="-10.795" y="7.62" drill="0.8" shape="long"/>
+<pad name="2" x="-10.795" y="5.08" drill="0.8" shape="long"/>
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+<rectangle x1="-1.905" y1="-13.97" x2="1.905" y2="-10.16" layer="21"/>
+<text x="-8.255" y="1.905" size="1.27" layer="21">GND</text>
+<text x="-8.255" y="-0.635" size="1.27" layer="21">!CS!</text>
+<text x="-8.255" y="-3.175" size="1.27" layer="21">CLKOUT</text>
+<text x="-8.255" y="-5.715" size="1.27" layer="21">!RST!</text>
+<text x="-8.255" y="-8.255" size="1.27" layer="21">!INT!</text>
+<text x="-8.255" y="4.445" size="1.27" layer="21">PoE-2</text>
+<text x="-8.255" y="6.985" size="1.27" layer="21">PoE-1</text>
+<text x="10.16" y="-8.255" size="1.27" layer="21" align="bottom-right">SDI</text>
+<text x="10.16" y="-5.715" size="1.27" layer="21" align="bottom-right">SDO</text>
+<text x="10.16" y="-3.175" size="1.27" layer="21" align="bottom-right">SCK</text>
+<text x="10.16" y="-0.635" size="1.27" layer="21" align="bottom-right">Vcc</text>
+<text x="10.16" y="1.905" size="1.27" layer="21" align="bottom-right">Vaux</text>
+<text x="10.16" y="4.445" size="1.27" layer="21" align="bottom-right">PoE+2</text>
+<text x="10.16" y="6.985" size="1.27" layer="21" align="bottom-right">PoE+1</text>
+</package>
+</packages>
+<symbols>
+<symbol name="IN28J60">
+<pin name="GND" x="17.78" y="7.62" length="middle" direction="pwr" rot="R180"/>
+<pin name="!CS!" x="17.78" y="-5.08" length="middle" direction="in" rot="R180"/>
+<pin name="CLKOUT" x="17.78" y="5.08" length="middle" direction="out" rot="R180"/>
+<pin name="!RST!" x="17.78" y="2.54" length="middle" direction="in" rot="R180"/>
+<pin name="!INT!" x="17.78" y="0" length="middle" direction="out" rot="R180"/>
+<pin name="VAUX" x="17.78" y="10.16" length="middle" rot="R180"/>
+<pin name="VCC" x="17.78" y="12.7" length="middle" direction="pwr" rot="R180"/>
+<pin name="SCK" x="17.78" y="-7.62" length="middle" direction="in" rot="R180"/>
+<pin name="SDO" x="17.78" y="-10.16" length="middle" direction="out" rot="R180"/>
+<pin name="SDI" x="17.78" y="-12.7" length="middle" direction="in" rot="R180"/>
+<pin name="POE-1" x="-15.24" y="7.62" length="middle" direction="out"/>
+<pin name="POE-2" x="-15.24" y="5.08" length="middle" direction="out"/>
+<pin name="POE+1" x="-15.24" y="10.16" length="middle" direction="out"/>
+<pin name="POE+2" x="-15.24" y="2.54" length="middle" direction="out"/>
+<wire x1="12.7" y1="-15.24" x2="12.7" y2="15.24" width="0.254" layer="94"/>
+<wire x1="12.7" y1="15.24" x2="-10.16" y2="15.24" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="15.24" x2="-10.16" y2="-15.24" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="-15.24" x2="12.7" y2="-15.24" width="0.254" layer="94"/>
+<text x="-10.16" y="-17.78" size="1.778" layer="94">&gt;NAME</text>
+<text x="-10.16" y="-20.32" size="1.778" layer="94">IN28J60</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="IN28J60" prefix="ETH">
+<description>Stand-alone Ethernet Controller Module</description>
+<gates>
+<gate name="G$1" symbol="IN28J60" x="25.4" y="-10.16"/>
+</gates>
+<devices>
+<device name="" package="DIL">
+<connects>
+<connect gate="G$1" pin="!CS!" pad="4"/>
+<connect gate="G$1" pin="!INT!" pad="7"/>
+<connect gate="G$1" pin="!RST!" pad="6"/>
+<connect gate="G$1" pin="CLKOUT" pad="5"/>
+<connect gate="G$1" pin="GND" pad="3"/>
+<connect gate="G$1" pin="POE+1" pad="14"/>
+<connect gate="G$1" pin="POE+2" pad="13"/>
+<connect gate="G$1" pin="POE-1" pad="1"/>
+<connect gate="G$1" pin="POE-2" pad="2"/>
+<connect gate="G$1" pin="SCK" pad="10"/>
+<connect gate="G$1" pin="SDI" pad="8"/>
+<connect gate="G$1" pin="SDO" pad="9"/>
+<connect gate="G$1" pin="VAUX" pad="12"/>
+<connect gate="G$1" pin="VCC" pad="11"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>
diff --git a/eagle/lbr/atmega/pem1300.lbr b/eagle/lbr/atmega/pem1300.lbr
new file mode 100755
index 0000000..4fcd92f
--- /dev/null
+++ b/eagle/lbr/atmega/pem1300.lbr
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
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+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
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+</layers>
+<library>
+<packages>
+<package name="SIL">
+<pad name="1" x="-25.4" y="0" drill="0.8" shape="long" rot="R90"/>
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+<pad name="7" x="17.78" y="0" drill="0.8" shape="long" rot="R90"/>
+<text x="-25.4" y="2.54" size="1.27" layer="21">1</text>
+<wire x1="-27.94" y1="6.35" x2="27.94" y2="6.35" width="0.127" layer="21"/>
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+<wire x1="27.94" y1="-10.16" x2="27.94" y2="6.35" width="0.127" layer="21"/>
+<wire x1="-27.94" y1="-10.16" x2="-27.94" y2="6.35" width="0.127" layer="21"/>
+<text x="-25.4" y="-2.54" size="1.27" layer="21" align="top-left">PEM1300</text>
+<text x="25.4" y="-2.54" size="1.27" layer="21" align="top-right">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="PEM1300">
+<pin name="VINA+" x="15.24" y="7.62" length="middle" direction="in" rot="R180"/>
+<pin name="VINA-" x="15.24" y="5.08" length="middle" direction="in" rot="R180"/>
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+<pin name="CP1" x="15.24" y="-5.08" length="middle" rot="R180"/>
+<pin name="CP2" x="15.24" y="-7.62" length="middle" rot="R180"/>
+<pin name="-VDC" x="-15.24" y="-5.08" length="middle" direction="pwr"/>
+<pin name="+VDC" x="-15.24" y="0" length="middle" direction="pwr"/>
+<pin name="OADJ" x="-15.24" y="5.08" length="middle"/>
+<wire x1="10.16" y1="10.16" x2="10.16" y2="-10.16" width="0.254" layer="94"/>
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+<wire x1="-10.16" y1="10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
+<text x="-10.16" y="-12.7" size="1.778" layer="94">&gt;NAME</text>
+<text x="-10.16" y="-15.24" size="1.778" layer="94">PEM1300</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="PEM1300" prefix="POE">
+<description>Power Over Ethernet PD Module</description>
+<gates>
+<gate name="G$1" symbol="PEM1300" x="40.64" y="-12.7"/>
+</gates>
+<devices>
+<device name="" package="SIL">
+<connects>
+<connect gate="G$1" pin="+VDC" pad="8"/>
+<connect gate="G$1" pin="-VDC" pad="7"/>
+<connect gate="G$1" pin="CP1" pad="5"/>
+<connect gate="G$1" pin="CP2" pad="6"/>
+<connect gate="G$1" pin="OADJ" pad="9"/>
+<connect gate="G$1" pin="VINA+" pad="1"/>
+<connect gate="G$1" pin="VINA-" pad="2"/>
+<connect gate="G$1" pin="VINB+" pad="3"/>
+<connect gate="G$1" pin="VINB-" pad="4"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MPN" value="PEM1303"/>
+<attribute name="OC_FARNELL" value="1902523"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>