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authorWilliam Harrington <kb0iic@berzerkula.org>2018-05-17 20:54:06 -0500
committerWilliam Harrington <kb0iic@berzerkula.org>2018-05-17 20:54:06 -0500
commit5851c4758d3301851cf58e0ec3b42c7f93c7ca77 (patch)
treecc5a864a539f8b453b336a16be9c37dcf0a5f221 /eagle/lbr/atmega/at24mac402.lbr
parent8854dc9392a1bf8bb4137874c1f24f6825e07fc6 (diff)
Populate repository from main eagle directory in user's document library.
Diffstat (limited to 'eagle/lbr/atmega/at24mac402.lbr')
-rwxr-xr-xeagle/lbr/atmega/at24mac402.lbr202
1 files changed, 202 insertions, 0 deletions
diff --git a/eagle/lbr/atmega/at24mac402.lbr b/eagle/lbr/atmega/at24mac402.lbr
new file mode 100755
index 0000000..30b039e
--- /dev/null
+++ b/eagle/lbr/atmega/at24mac402.lbr
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
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+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
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+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
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+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
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+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<packages>
+<package name="PDIP">
+<pad name="1" x="-2.54" y="3.81" drill="0.8" shape="long"/>
+<pad name="2" x="-2.54" y="1.27" drill="0.8" shape="long"/>
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+<text x="-5.08" y="5.08" size="1.27" layer="21">&gt;NAME</text>
+</package>
+<package name="SOIC127P600X175-8N">
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+<text x="-3.2004" y="2.3368" size="1.27" layer="51" ratio="6" rot="SR0">*</text>
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+<text x="-4.699" y="3.429" size="2.0828" layer="25" ratio="10" rot="SR0">&gt;NAME</text>
+<text x="-5.3848" y="-5.0038" size="2.0828" layer="27" ratio="10" rot="SR0">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="AT24MAC402">
+<pin name="VCC" x="-15.24" y="7.62" length="middle" direction="pwr"/>
+<pin name="A0" x="-15.24" y="2.54" length="middle" direction="in"/>
+<pin name="A1" x="-15.24" y="0" length="middle" direction="in"/>
+<pin name="A2" x="-15.24" y="-2.54" length="middle" direction="in"/>
+<pin name="WP" x="-15.24" y="-7.62" length="middle" direction="in"/>
+<pin name="GND" x="-15.24" y="-12.7" length="middle" direction="pwr"/>
+<pin name="SDA" x="15.24" y="7.62" length="middle" rot="R180"/>
+<pin name="SCL" x="15.24" y="0" length="middle" direction="in" rot="R180"/>
+<wire x1="-10.16" y1="12.7" x2="-10.16" y2="-17.78" width="0.4064" layer="94"/>
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+<text x="-4.7244" y="14.1986" size="2.0828" layer="95" ratio="10" rot="SR0">&gt;NAME</text>
+<text x="-5.6642" y="-21.3614" size="2.0828" layer="96" ratio="10" rot="SR0">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="24MAC402-SSHM-T" prefix="U">
+<description>EEPROM, SERIAL, 2KB, 48-BIT MAC, 8SOIC</description>
+<gates>
+<gate name="A" symbol="AT24MAC402" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SOIC127P600X175-8N">
+<connects>
+<connect gate="A" pin="A0" pad="1"/>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="GND" pad="4"/>
+<connect gate="A" pin="SCL" pad="6"/>
+<connect gate="A" pin="SDA" pad="5"/>
+<connect gate="A" pin="VCC" pad="8"/>
+<connect gate="A" pin="WP" pad="7"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MPN" value="24MAC402-SSHM-T" constant="no"/>
+<attribute name="OC_FARNELL" value="2134868" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+<attribute name="PACKAGE" value="8SOIC" constant="no"/>
+<attribute name="SUPPLIER" value="ATMEL" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="PDIP" package="PDIP">
+<connects>
+<connect gate="A" pin="A0" pad="1"/>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="GND" pad="4"/>
+<connect gate="A" pin="SCL" pad="6"/>
+<connect gate="A" pin="SDA" pad="5"/>
+<connect gate="A" pin="VCC" pad="8"/>
+<connect gate="A" pin="WP" pad="7"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>